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Integrated L1-Band GPS Receiver
Detailed Register Definitions
Table 4. Detailed Register Definition for Write Address 0100: SYNTH
DATA BIT
D15
D14
D13–D10
D9
D8
D7–D0
DEFAULT
1
1
0100
1
0
01100000
DESCRIPTION
Reserved
LPF Autotune Initiate: I = Initiate autotune, 0 = Manual tuning.
LPF Tuning Word: 0000 ~ 7.7MHz, 1111 ~ 2.9MHz.
XTAL Clock Select: 1 = External reference, 0 = Synthesized 16.8MHz.
Standby: 0 = Normal operating mode, 1 = Standby (oscillator remains active), but only if D9 = 1.
Reference Division Ratio. Default 19.2MHz external reference (R = 96dec). R = f REF / 200kHz.
Table 5. Detailed Register Definition for Write Address 0101: CONFIG 1
DATA BIT
D15
D14–D11
D10
D9 to D8
D7 to D5
D4–D0
DEFAULT
1
0000
0
00
001
11111
DESCRIPTION
ADC Mode. Select 1 for 1-bit magnitude and sign, select 0 for 2-bit magnitude and sign.
1: GPSIF2 = sign, GPSIF1 = magnitude, GPSIF0 = X
0: GPSIF2 = MSB magnitude, GPSIF1 = LSB magnitude, GPSIF0 = sign
ADC Offset Control (approx 4mV/step): D14 = LSB, D12 = MSB, D11 = sign.
Double Charge-Pump Current: 0 = 100μA, 1 = 200μA.
Digital Test Bus Mode Select. See Table 9 for test-mode descriptions.
VCO Coarse Tuning Range. 000 = Lowest frequency, 111 = Highest frequency.
AGC Gain. Digital control of the AGC amplifier in the 2nd IF section. 00000 => min gain, 11111 =>
max gain (linear gain ~2.5dB per unit SPI word).
Table 6. Detailed Register Definition for Write Address 0110: CONFIG 2
DATA BIT
D15
D14
D13
D12–D7
D6 to D5
D4–D0
DEFAULT
1
1
1
100000
11
11111
DESCRIPTION
Reset CMOS: 0 = Hold CMOS dividers in reset and PFD is tri-stated, 1 = Inactive.
Drive VCO Low: 0 = Active, forces VCO to lowest frequency.
N.B. do not activate both D14 and D13 at the same time.
Drive VCO High: <forces LCP low FET on, driving V TUNE low, forcing VCO to highest extreme> 0 =
Active, forces VCO to highest frequency. N.B. do not activate both D14 and D13 at the same time.
Reserved
Must be programmed to 11
Analog Test Mode Select: Reserved
8
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